1. Field of the Invention
The present invention relates to voltage drivers, and more particularly to a MOSFET driver for interfacing a digital circuit to a bus subject to overvoltage conditions.
2. Description of Related Art
Input/output ("I/O") circuits are commonly used to interface digital circuits to a common bus. FIG. 1 shows a typical I/O circuit 100 that includes a pullup/pulldown circuit 110, an input buffer 176 comprising inverters 172 and 174 for furnishing signals from the bus to a digital circuit, an enable circuit 130 responsive to an enable signal on terminal 104 for placing the pullup/pulldown circuit 110 in a high impedance state or for controlling the operation of pullup/pulldown circuit 110 in accordance with the logic state of a signal on the data input terminal 105, and I/O terminal 170 which connects to the bus.
Pullup/pulldown circuit 110 includes P-channel MOSFET 111 having a gate connected to the enable circuit 130, a source connected to V.sub.dd voltage Supply rail 120, a drain connected to I/O terminal 170, and a body connected to V.sub.dd rail 120. Pullup/pulldown circuit 110 also includes N-channel MOSFET 112 having a gate connected to the enable circuit 130, a drain connected to the I/O terminal 170, a source connected to ground rail 140, and a body connected to ground rail 140.
When the enable signal EN is HIGH, I/O circuit 100 is in output mode. NAND gate 103 and NOR gate 102 apply the inverse of the logic state of signal DATA.sub.-- IN to the gate of MOSFET 111 and to the gate of MOSFET 112. When the input signal DATA.sub.-- IN is HIGH, MOSFET 111 is ON to maintain a current path between V.sub.dd rail 120 and I/O terminal 170 to drive the data bus HIGH, while MOSFET 112 is OFF to isolate the I/O terminal 170 from the ground rail 140. Alternatively, when DATA.sub.-- IN is LOW, MOSFET 111 is OFF to isolate V.sub.dd rail 120 from I/O terminal 170, while MOSFET 112 is ON to maintain a current path between the I/O terminal 170 and the ground rail 140 to pull the data bus LOW.
When EN is LOW, the I/O circuit 100 is in a high impedance mode. NAND gate 103 applies a HIGH voltage to the gate of MOSFET 111, and NOR gate 102 applies a LOW voltage to the gate of MOSFET 112. MOSFET 111 is OFF to isolate the V.sub.dd rail 120 from I/O terminal 170, and MOSFET 112 is OFF to isolate I/O terminal 170 from ground rail 140. The pullup/pulldown circuit 110 is therefore in a high impedance state so that logic signals present on I/O terminal 170 are furnished to terminal 178, unaffected by the DATA.sub.-- IN signal on terminal 105.
With the development of 3.3 volt logic circuits, interfacing 3.3 volt and 5.0 volt circuits on the same bus became desirable. Unfortunately, interfacing 3.3 volt digital circuits using the conventional I/O circuit shown in FIG. 1 to a bus driven by a 5.0 volt digital circuit results in current leakage from the 5.0 volt data bus through the channel region and the parasitic drain-body and source-body junction diodes of MOSFET 111 into V.sub.dd rail 120. While the amount of the leakage current is process and device dependant, the leakage is undesirable for a number of reasons. Leakage increases power consumption, leads to the generation of excessive heat which reduces integrated circuit reliability, and if excessive, significantly loads the 5.0 volt bus which reduces the noise margin.